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intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet the intel ? lxt901a and lxt907a transceivers (called hereafter the lxt901a/907a transceivers) are new generation universal ethernet transceivers with improved noise immunity and output filtering. the feature set of the lxt901a/907a has been streamlined, removing remote signaling capabilities. the lxt901a and lxt907a provide all the active circuitry to interface most standard ieee 802.3 controllers to either the 10base-t media or attachment unit interface (aui). the lxt901a and lxt907a transceivers are identical except for the function of one pin. the lxt901a transceiver, with selectable termination impedance, allows the use of either shielded or unshielded twisted-pair cable. the lxt907a transceiver offers a signal quality error disable (dsqe) function. the lxt901a/907a transceivers functions include manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link testing, and reversed polarity detection/ correction. applications product features access devices (dsl, cable modems, and set-top boxes) routers/bridges/switches/hubs telecom backplane usb to ethernet converters functional features integrated filters - simplify fcc compliance integrated manchester encoder/decoder 10base-t transceiver aui transceiver full-duplex capable (20 mbps) diagnostic features four led drivers aui/rj-45 loopback convenience features automatic/manual aui/rj-45 selection automatic polarity correction sqe disable function ( lxt907a transceiver ) programmable impedance driver ( lxt901a transceiver ) single 3.3v operation power-down mode and four loopback modes available in 64-pin lqfp and 44-pin plcc packages commercial (0 to +70 o c) order number: 249098-003 27-nov-2005
2 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. the intel ? lxt901a/907a universal 3.3 v ethernet transceiver may contain design defects or errors known as errata which may cause the pro duct to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation. all rights reserved.
datasheet 3 document number: 249098 revision number: 003 revision date: 27-nov-2005 contents contents 1.0 pin assignments and signal descriptions ....................................................................8 2.0 functional description ..................................................................................................12 2.1 controller compatibility modes ........................................................................... 12 2.2 transmit function................................................................................................13 2.2.1 jabber control function .........................................................................13 2.2.2 sqe function .........................................................................................14 2.2.2.1 sqe disable function (lxt907a transceiver only) ................. 14 2.3 receive function.................................................................................................15 2.3.1 polarity reverse function ......................................................................15 2.3.2 collision detection function...................................................................16 2.4 loopback functions ............................................................................................17 2.4.1 standard tp loopback........................................................................... 17 2.4.2 forced tp loopback ..............................................................................17 2.4.3 aui loopback......................................................................................... 17 2.4.4 external loopback.................................................................................. 17 2.5 link integrity test function .................................................................................17 2.6 link pulse transmission .....................................................................................19 3.0 application information .................................................................................................19 3.1 twisted-pair impedance matching ......................................................................19 3.2 crystal information ..............................................................................................19 3.3 magnetics information ......................................................................................... 19 3.4 typical applications.............................................................................................20 3.4.1 auto port select with external loopback control................................... 20 3.4.2 full-duplex support................................................................................ 22 3.4.3 dual network support - 10base-t and token ring ...............................23 3.4.4 manual port select with link test function ........................................... 24 3.4.5 three media application.........................................................................26 3.4.6 aui encoder/decoder only .................................................................... 27 3.4.7 150w shielded twisted-pair only (lxt901a transceiver only) ............ 28 4.0 test specifications .........................................................................................................29 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) figures 17 - 22 ............33 4.2 timing diagrams for mode 2 (md1 = low, md0 = high) figures 23 - 28 ...........35 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) figures 29 - 36 ...........37 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) figures 37 - 42 ..........40 5.0 mechanical specifications .............................................................................................42 5.1 top-label marking .............................................................................................. 44 6.0 ordering information .....................................................................................................47
contents 4 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 figures 1 intel ? lxt901a/907a transceiver block diagram................................................ 7 2 intel ? lxt901a and lxt907a transceiver pin assignments .............................. 8 3 tpo output waveform .......................................................................................13 4 jabber control function ..................................................................................... 14 5 sqe function .....................................................................................................15 6 collision detection function ............................................................................... 16 7 link integrity test function ................................................................................ 18 8 transmitted link integrity pulse timing ............................................................. 19 9 lan adapter board - auto port select with external l pbk control ..................21 10 full-duplex operation ........................................................................................ 22 11 380c26 interface for dual network support of 10 base-t and token ring ...... 23 12 lan adapter board - manual port select with link test function...................... 24 13 manual port select with seeq 8005 controller .................................................. 25 14 three media application .................................................................................... 26 15 aui encoder/decoder only application ............................................................. 27 16 150 w shielded twisted-pair only application (lxt901a transceiver ) ........... 28 17 mode 1 rclk/start-of-frame timing ................................................................ 33 18 mode 1 rclk/end-of-frame timing .................................................................. 33 19 mode 1 transmit timing .................................................................................... 34 20 mode 1 collision detect timing ......................................................................... 34 21 mode 1 col/ci output timing ...........................................................................34 22 mode 1 loopback timing ................................................................................... 34 23 mode 2 rclk/start-of-frame timing ................................................................ 35 24 mode 2 rclk/end-of-frame timing .................................................................. 35 25 mode 2 transmit timing .................................................................................... 36 26 mode 2 collision detect timing ......................................................................... 36 27 mode 2 col/ci output timing ...........................................................................36 28 mode 2 loopback timing ................................................................................... 36 29 mode 3 rclk/start-of-frame timing (lxt901a transceiver) .......................... 37 30 mode 3 rclk/end-of-frame timing (lxt901a transceiver) ........................... 37 31 mode 3 rclk/start-of-frame timing (lxt907a transceiver) .......................... 38 32 mode 3 rclk/end-of-frame timing (lxt907a transceiver) ........................... 38 33 mode 3 transmit timing .................................................................................... 39 34 mode 3 collision detect timing .......................................................................... 39 35 mode 3 col/ci output timing ...........................................................................39 36 mode 3 loopback timing ................................................................................... 39 37 mode 4 rclk/start-of-frame timing ................................................................. 40 38 mode 4 rclk/end-of-frame timing .................................................................. 40 39 mode 4 transmit timing .................................................................................... 41 40 mode 4 collision detect timing ......................................................................... 41 41 mode 4 col/ci output timing ...........................................................................41 42 mode 4 loopback timing ................................................................................... 41 43 44-pin plcc ....................................................................................................... 42 44 64-pin lqfp ...................................................................................................... 43 45 sample lqfp package ? intel ? djlxt901alc transceiver ............................. 44 46 sample pb-free (rohs-compliant) lqfp package ? intel ? wjlxt901alc transceiver......................................................................44 47 sample tqfp package ? intel ? djlxt907alc transceiver ............................. 45
datasheet 5 document number: 249098 revision number: 003 revision date: 27-nov-2005 contents 48 sample pb-free (rohs-compliant) tqfp package ? intel ? wjlxt907alc transceiver ...................................................................... 45 49 sample plcc package ? intel ? nlxt90xapc transceiver...............................46 50 sample pb-free (rohs-compliant) plcc package ? intel ? eelxt90xapc transceiver ......................................................................46 51 ordering information matrix ? sample ................................................................48 tables 1 signal descriptions................................................................................................ 9 2 controller compatibility modes ........................................................................... 12 3 suitable crystals .................................................................................................19 4 absolute maximum values..................................................................................29 5 recommended operating conditions ................................................................. 29 6 i/o electrical characteristics ...............................................................................29 7 aui electrical characteristics ..............................................................................30 8 tp electrical characteristics ...............................................................................30 9 switching characteristics ....................................................................................31 10 rclk/start-of-frame timing...............................................................................31 11 rclk/end-of-frame timing................................................................................32 12 transmit timing...................................................................................................32 13 collision, col/ci output and loopback timing.................................................. 32 14 product information ............................................................................................. 47
contents 6 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 revision history date revision page description 27-nov-2005 003 8 updated figure 2 ?intel? lxt901a and lxt907a transceiver pin assignments? on page 8 . 44 added section 5.1, ?top-label marking? on page 44 . 47 modfied table 14 ?product information? on page 47 . 48 modified figure 51 ?ordering information matrix ? sample? on page 48 . june 2001 002 1 new items under ?applications? 23 figure 9: added 0.1 f label to capacitor at bottom of graphic. 24 figure 10: added 0.1 f label to capacitor at bottom of graphic. 25 figure 11added 0.1 f label to capacitor at bottom of graphic. 26 figure 12: added 0.1 f label to capacitor at bottom of graphic. 27 figure 13: added 0.1 f label to capacitor at bottom of graphic. 31 added 2nd para under test specification regarding quality and reliability information. 31 removed ?ambient operating temperature? from absolute maximum values table. 45 added appendix: product ordering information
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 7 document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 1. intel ? lxt901a/907a transceiver block diagram mode select logic controller compatibility port select loopback link test squelch / link detect manchester decoder collision logic watchdog timer xtal osc manchester encoder select: pls only or pls / mau do autosel paui lbk li tclk clko clki ten txd cd ledl md0 tpopa tpona tponb tpip tpin pulse shaper and filter twisted pair interface collision/ polarity detect correct rc rc di lpbk collision receiver rxd rclk col ci md1 tpopb dop don dip din cip cin ledr ledt/ pdn ledc/fde nth jab plr + - drop cable interface ecl tx amp rx slicer rx slicer cmos tx amp dsqe (lxt907a only) (lxt901a onl y) stp
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 8 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 1.0 pin assignments and signal descriptions figure 2. intel ? lxt901a and lxt907a transceiver pin assignments 7 8 9 10 11 12 13 14 15 16 17 n/c li jab test tclk txd ten clko clki col autosel tpin tpip dsqe (907a) or stp (901a ) tponb tpona vcc2 gnd2 tpopa tpopb plr n/c 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 ledr ledt/pdn ledl ledc/fde lbk gnd1 rbias n/ c rxd cd rclk md 1 md 0 nth cin cip vcc1 don dop din dip pa ui 6 5 4 3 2 1 44 43 42 41 40 lxt901a/907apc xx xxxxxxxx part # fpo # rev # bsmc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n/c n/c paui dip din n/c dop don v cca v cc1 cip cin nth md0 md1 n/c n/c n/c tpin tpip n/c ds qe (9 07 a) or stp (901 a ) tponb tpona vcc2 gnd2 tpopa tpopb plr n/c n/c n/c 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 n/c n/c li n/c jab te st tc l k txd ten clko clki co l a utosel n/c n/c n/c n/c rclk cd rxd n/c n/c rbias n/c gnda gnd1 lbk ledc/fd e ledl ledt/pd n ledr n/c 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lxt901a/907alc xx xxxxxxxx part # fpo # rev # 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 bsmc
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 9 document number: 249098 revision number: 003 revision date: 27-nov-2005 table 1. signal descriptions pin # symbol i/o 1 description plcc lqfp 1 34 10 56 vcc1 vcc2 ? ? power supply 1 and 2. power supply inputs of +3.3 volts. ? 9 vcca ? analog supply. (+3.3v) 2 3 11 12 cip cin i i aui collision pair. differential input to the aui transceiver ci circuit. the input is collision signaling or sqe. 413 nthi normal threshold. selects normal or reduced threshold. when nth is high, the normal tp squelch threshold is in effect. when nth is low, the normal tp squelch threshold is reduced by 4.5 db. 5 6 14 15 md0 md1 i i mode select 0 (md0) and mode select 1 (md1). mode select pins determine the controller compatibility mode in accordance with table 2 . 819 li i link test enable. controls link integrity test; enabled when li = high, disabled when li = low 921 jabo jabber indicator. output goes high to indicate jabber state. 10 22 test i test. for intel internal use only. it is recommended to tie this pin high externally. 11 23 tclk o transmit clock. a 10 mhz clock output. this clock signal should be directly connected to the transmit clock input of the controller. 12 24 txd i transmit data. input signal containing nrz data to be transmitted on the network. connect txd directly to the transmit data output of the controller. 13 25 ten i transmit enable. enables data transmission and starts the watchdog timer. synchronous to tclk (see test specifications for details). 14 15 26 27 clko clki o i crystal oscillator. a 20 mhz crystal must be connected across these pins, or a 20 mhz clock applied at clki with clko left open. 16 28 col o collision detect. output which drives the collision detect input of the controller. 17 29 autosel i automatic port select. when high, automatic port selection is enabled (the 901a/907a defaults to the aui port only if tp link integrity = fail). when low, manual port selection is enabled (the paui pin determines the active port). 18 34 ledr od receive led. open drain driver for the receive indicator led. output is pulled low during receive. 19 35 ledt/ pdn od transmit led (ledt)/power-down (pdn ). open drain driver for the transmit indicator. output is pulled low during transmit. do not allow this pin to float. if unused, tie high. if externally pulled low, the lxt901a/907a goes to power-down state. 20 36 ledl od link led. open drain driver for link integrity indicator. output is pulled low during link test pass. if externally tied low, internal circuitry is forced to ?link pass? state and the lxt901a/907a transceiver transmits link test pulses continuously. 1. i/o column coding: i = input, o = output, od = open drain
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 10 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 21 37 ledc/ fde od collision led (ledc)/full-duplex enable (fde ). open drain driver for the collision indicator pulls low during collision. led ?on? (i.e., low output) time is extended by approximately 100 ms. if externally tied low, enables full-duplex operation by disabling the internal tp loopback and collision detection circuits in anticipation of external twisted-pair loopback or full-duplex operation. if this pin is not used, tie high or directly to vcc. 22 38 lbk i loopback. enables internal loopback mode. refer to functional description for details. 23 33 39 55 gnd1 gnd2 ? ? ground returns 1 and 2. grounds ? 40 gnda ? analog ground. 24 42 rbias i bias control. a 12.4 k 1% resistor to ground at this pin controls operating circuit bias. 26 45 rxd o receive data. output signal. connect directly to the receive data input of the controller. 27 46 cd o carrier detect. an output to notify the controller of activity on the network. 28 47 rclk o receive clock. a recovered 10 mhz clock that is synchronous to the received data. connect to the controller receive clock input. 30 52 plr o polarity reverse. output goes high to indicate reversed polarity at the twisted- pair input. 31 36 32 35 53 58 54 57 tpopb tponb tpopa tpona o o o o twisted-pair transmit pairs a & b. two differential driver pair outputs (a and b) to the twisted-pair cable. the outputs are pre-equalized. each pair must be shorted together and tied to the transformer through a 24.9 1% series resistor to match impedance of 100 . refer to figure 16 on page 28 in the applications section for information on 150 configurations. 37 59 stp i stp select (lxt901a transceiver only). when stp is low, 150 termination for shielded twisted-pair is selected. when stp is high, 100 termination for unshielded twisted-pair is selected. lxt907a transceiver is designed for 100 unshielded twisted-pair termination (not selectable). dsqe i disable sqe (lxt907a transceiver only). when dsqe is high, the sqe function is disabled. when dsqe is low, the sqe function is enabled. sqe must be disabled for normal operation in hub/switch applications. the lxt901a transceiver operates with sqe enabled (not selectable). 38 39 61 62 tpip tpin i i twisted-pair receive pair. a differential input pair from the twisted-pair cable. receive filter is integrated on-chip. no external filters are required. 40 3 paui i port/aui select. in manual port select mode (autosel low), paui selects the active port. when paui is high, the aui port is selected. when paui is low, the tp port is selected. in auto port select mode, paui must be tied to ground. table 1. signal descriptions (continued) pin # symbol i/o 1 description plcc lqfp 1. i/o column coding: i = input, o = output, od = open drain
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 11 document number: 249098 revision number: 003 revision date: 27-nov-2005 41 42 4 5 dip din i i aui receive pair. differential input pair from the aui transceiver di circuit. the input is manchester encoded. 43 44 7 8 dop don o o aui transmit pair. a differential output driver pair for the aui transceiver cable. the output is manchester encoded. 7, 25, 29 1, 2, 6, 16, 17, 18, 20, 30, 31, 32, 33, 41, 43, 44, 48, 49, 50, 51, 60, 63, 64 n/c ? no connect (internally tied to ground). table 1. signal descriptions (continued) pin # symbol i/o 1 description plcc lqfp 1. i/o column coding: i = input, o = output, od = open drain
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 12 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 2.0 functional description the lxt901a/907a transceiver performs the physical layer signaling (pls) and media attachment unit (mau) functions as defined by the ieee 802.3 specification. they function as a pls-only device (for use with 10base-2 or 10base-5 coaxial cable networks) or as an integrated pls/mau (for use with 10base-t twisted-pair networks). in addition to standard 10 mbps operation, they also support full-duplex 20 mbps operation. the lxt901a/907a transceiver interfaces a back-end controller to either an aui drop cable or a twisted-pair (tp) cable. the controller interface includes a transmit and receive clock and nrz data channels, as well as mode control logic and signaling. the aui interface comprises three circuits: data output (do), data input (di) and collision (ci). the twisted-pair interface is comprised of two circuits: twisted-pair input (tpi) and twisted-pair output (tpo). in addition to the three basic interfaces, the lxt901a/907a transc eiver contains an internal crystal oscillator and four led drivers for visual status reporting. functions are defined from the back-end controller side of the interface. the transmit function refers to data transmitted by the back-end to the aui cable (pls-only mode) or to the twisted-pair network (integrated pls/mau mode). the receive function refers to data received by the back- end from the aui cable (pls-only) or from the twisted-pair network (integrated pls/mau mode). in the integrated pls/mau mode, the lxt901a/907a transceiver performs all required mau functions defined by the ieee 802.3 10base?t specification, such as collision detection, link integrity testing, signal quality error messaging, jabber control, and loopback. in the pls-only mode, the lxt901a/907a transceiver receives incoming signals from the aui di circuit, with 18 ns of jitter, and drives the aui do circuit. 2.1 controller compatibility modes the lxt901a/907a transceiver are compatible with most industry standard controllers, including devices produced by motorola*, amd*, intel, fujitsu*, national semiconductor*, seeq*, and texas instruments*. four different control signal timing and polarity schemes (modes 1 through 4) are required to achieve this compatibility. mode select pins (md0 and md1) determine controller compatibility modes as listed in table 2 . refer to test specifications for a complete set of timing diagrams for each mode. table 2. controller compatibility modes controller mode setting md1 md0 mode 1 for motorola 68en360, mpc860, advanced micro devices am7990 or compatible controllers low low mode 2 for intel 82596 or compatible controllers 1 low high
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 13 document number: 249098 revision number: 003 revision date: 27-nov-2005 2.2 transmit function the lxt901a/907a transceiver receives nrz data from the controller at the txd input, as shown in figure 1, ?intel? lxt901a/907a transceiver block diagram? on page 7 , and passes it through a manchester encoder. the encoded data is then transferred to either the aui cable (the do circuit) or the twisted-pair network (the tpo circuit). the advanced integrated pulse shaping and filtering network produces the output signal on tpon and tpop as shown in figure 3 . the tpo output is pre-distorted and pre-filtered to meet the 10base-t jitter template. an internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. integrated filters simplify the design work required for fcc compliant emi performance. during idle periods, the lxt901a/907a transceiver transmits link integrity test pulses on the tpo circuit (if li is enabled and integrated, pls/ mau mode is selected). external resistors control the termination impedance for the lxt907a transceiver. external resistors and the stp pin control termination impedance on the lxt901a transceiver. 2.2.1 jabber control function figure 4 is a state diagram of the lxt901a/907a transceiver jabber control function. the on-chip watchdog timer prevents the dte from locking into a continuous transmit mode. when a transmission exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and activates the jab pin. once the lxt901a/907a transceiver is in the jabber state, the txd circuit must remain idle for a period of 250 to 750 ms before it exits the jabber state. mode 3 for fujitsu mb86950, mb86960 or compatible controllers (seeq 8005) 2 high low mode 4 for national semiconductor 8390 or compatible controllers (ti tms380c26) high high 1. refer to intel application note 51 when designing with intel controllers. 2. seeq controllers require inverters on clk1, lbk, rclk and col. table 2. controller compatibility modes controller mode setting md1 md0 figure 3. tpo output waveform
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 14 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 2.2.2 sqe function in the integrated pls/mau mode, the lxt901a/907a transceiver supports the signal quality error (sqe) function as shown in figure 5 on page 15 , although the sqe function can be disabled on the lxt907a transceiver. after every successful transmission on the 10base-t network, when sqe is enabled, the lxt901a/907a transceiver transmits the sqe signal for 10 bit times 5 bit times over the internal ci circuit, which is indicated on the col pin of the device. when using the aui of the lxt901a/907a transceiver, the sqe function is determined by the external mau attached. 2.2.2.1 sqe disable function (lxt907a transceiver only) sqe must be disabled for normal operation in hub and switch applications. the lxt907a transceiver is configured with an sqe disable function. the sqe function is disabled when dsqe is set high, and enabled when dsqe is low. figure 4. jabber control function no output nonjabber output start_xmit_max_timer power on do=active jab xmit=disable lpbk=disable ci=sqe unjab wait start_unjab_timer xmit=disable lpbk=disable ci=sqe do=active ? xmit_max_timer_done do=idle do=idle unjab_ timer_done do=active ? unjab_timer_not_done
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 15 document number: 249098 revision number: 003 revision date: 27-nov-2005 2.3 receive function the lxt901a/907a transceiver receive function acquires timing and data from the twisted-pair network (the tpi circuit) or from the aui (the di circuit). valid received signals are passed through the on-chip filters and manchester decoder, then output as decoded nrz data and receive timing on the rxd and rclk pins, respectively. an internal rc filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. the receive function is activated only by valid data streams above the squelch level and with proper timing. if the differential signal at the tpi or the di circuit inputs falls below 75 percent of the threshold level (unsquelched) for 8 bit times (typical), the lxt901a/907a transceiver receive function enters the idle state. if the polarity of the tpi circuit is reversed, lxt901a/907a transceiver detects the polarity reverse and reports it via the plr output. the lxt901a/907a transceiver automatically corrects reversed polarity. 2.3.1 polarity reverse function the lxt901a/907a transceiver polarity reverse function uses both link pulses and end-of-frame data to determine the polarity of the received signal. a reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. reversed polarity is also detected if four frames are received with a reversed start-of-idle. whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. if the lxt901a/907a transceiver enters the link fail state and no valid data or link pulses figure 5. sqe function output idle output detected power on do=active sqe wait test start_sqe_test__wait_timer sqe test start_sqe_test_timer ci=sqe sqe_test__wait_timer_done ? xmit=enable do=idle sqe_test_timer_done xmit=disable
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 16 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. if link integrity testing is disabled, polarity detection is based only on received data. polarity correction is always enabled. 2.3.2 collision detection function the collision detection function operates on the twisted- pair side of the interface. for standard (half-duplex) 10base-t operation, a collision is defined as the simultaneous presence of valid signals on both the tpi circuit and the tpo circuit. the lxt901a/907a transceiver reports collisions to the back-end via the col pin. if the tpi circuit becomes active while there is activity on the tpo circuit, the tpi data is passed to the back-end over the rxd circuit, disabling normal loopback. figure 6 on page 16 is a state diagram of the lxt901a/907a transceiver collision detection function. refer to test specifications for collision detection and col/ci output timing. note: for full-duplex operation on the tp or aui port, the collision detection circuitry must be disabled by setting fde low. figure 6. collision detection function idle power on a collision tpo=do di=tpi ci=sqe output tpo=do di=do input di=tpi do=active ? tpi=idle ? xmit=enable do=active ? tpi=active ? xmit=enable a a do=active ? tpi=active ? xmit=enable do=active ? tpi=idle do=idle+ xmit=disable do=idle tpi=idle tpi=active
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 17 document number: 249098 revision number: 003 revision date: 27-nov-2005 2.4 loopback functions 2.4.1 standard tp loopback the lxt901a/907a transceiver provides the standard loopback function defined by the 10base-t specification for the twisted-pair port. the loopback function operates in conjunction with the transmit function. data transmitted by the back-end is internally looped back within the lxt901a/907a transceiver from the txd pin through the manchester encoder/decoder to the rxd pin and returned to the back-end. this standard loopback function is disabled when a data collision occurs, clearing the rxd circuit for the tpi data. standard loopback is also disabled during link fail and jabber states. the lxt901a/907a transceiver also provides three additional loopback functions. 2.4.2 forced tp loopback ?forced? twisted-pair loopback is controlled by the lbk pin. when the twisted-pair port is selected and lbk is high, twisted-pair loopback is ?forced?, overriding collisions on the twisted- pair circuit. when lbk is low, normal loopback is in effect. 2.4.3 aui loopback aui loopback is also controlled by the lbk pin. when the aui port is selected and lbk is high, data transmitted by the back-end is internally looped back from the txd pin through the manchester encoder/decoder to the rxd pin. when lbk is low, no aui loopback occurs. 2.4.4 external loopback an external loopback mode, useful for system-level testing, is controlled by the ledc/fde pin. when ledc/fde is tied low, the lxt901a/907a transceiver disables the collision detection and internal loopback circuits, to allow external loopback. external loopback mode can be set on either twisted-pair or aui ports. 2.5 link integrity test function figure 7 on page 18 is a state diagram of the lxt901a/907a transceiver link integrity test function. the link integrity test is used to determine the status of the receive side twisted-pair cable. link integrity testing is enabled when the li pin is tied high. when enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. if no serial data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. the lxt901a/907a transceiver ignores any link integrity pulse with an interval less than 2 - 7 ms. the lxt901a/907a transceiver remains in the link fail state until it detects either a serial data packet or two or more link integrity pulses.
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 18 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 7. link integrity test function idle test start_link_loss_timer start_link_test_min_timer power on link test fail reset link_count=0 xmit=disable rcvr=disable link_loss_timer_done ? tpi=idle ? link_test_rcvd=false tpi=active+ (link_test_rcvd=true ? link_test_min_timer_done) link test fail wait xmit=disable rcvr=disable lpbk=disable link_count=link_count + 1 link test fail start_link_test_min_timer start_link_test_max_timer xmit=disable rcvr=disable lpbk=disable link_test_rcvd=false ? tpi=idle tpi=active tpi=active link_test_rcvd=idle ? tpi=idle link test fail extended xmit=disable rcvr=disable lpbk=disable tpi=active + link_count=lc_max link_test_min_timer_done ? link_test_rcvd=true (tpi=idle ? link_test_max_timer_done) + (link_test_min_timer_not_done ? link_test_rcvd=true) tpi=idle ? do=idle
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 19 document number: 249098 revision number: 003 revision date: 27-nov-2005 2.6 link pulse transmission when not transmitting data, the lxt901a/907a transceiver transmits ieee 802.3-compliant standard link pulses. figure 8 shows the link integrity pulse timing. 3.0 application information 3.1 twisted-pair impedance matching resistors must be installed on each input and output pair to match impedance of the network media being used. the lxt907a transceiver is configured with 100 termination for unshielded twisted-pair (utp). in this case, the positive and negative sides of both output pairs are shorted together (tpopa/tpopb and tpona/tponb) and tied to the transformer through a 24.9 1% series resistor. the lxt901a transceiver is designed with an stp select pin that allows the device to match both 100 and 150 media. a dual resistor combination can be configured to accommodate either line termination as shown in figure 16 on page 28 . when 100 termination is selected, both a and b pairs are driven in parallel. when 150 termination is selected, the b pair is tri-stated and only the a pair is driven. 3.2 crystal information designers should test and validate crystals before committing to a specific component. based on limited evaluation, table 3 lists some suitable crystals. 3.3 magnetics information the lxt901a/lxt907a transceiver requires a 1:1 ratio for the receive transformer and a 1: 2 ratio for the transmit transformer on the twisted-pair interface. the aui interface requires a 1:1 ratio for the data-in, data-out, and collision-pair transformers. a cross-reference list of suitable figure 8. transmitted link integrity pulse timing 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms table 3. suitable crystals manufacturer part number mtron mp-1 mp-2
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 20 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 magnetics and part numbers is available in application note 73, magnetic manufacturers (248991- 001), which can be found on the intel web site (developer.intel.com/design/network/). designers must test and validate all components for suitability in their applications. 3.4 typical applications figure 9 on page 21 through figure 16 on page 28 show typical lxt901a/907a transceiver applications. 3.4.1 auto port select with external loopback control figure 9 on page 21 is a typical lxt901a/907a transceiver application. the diagram groups similar pins together, but does not represent the actual lxt901a/907a transceiver pinout. the controller interface pins (transmit data, clock and enable; receive data and clock; and the collision detect, carrier detect and loopback control pins) are shown at the top left of the diagram. programmable option pins are grouped at the center left of the diagram. the paui pin is tied low and all other option pins are tied high. this setup selects the following options: ? automatic port selection (paui low and autosel high) ? normal receive threshold (nth high) ? mode 4, compatible with national ns8390 controllers (md0 high, md1 high) ? sqe disabled (dsqe high for lxt907a transceiver only) ? utp is selected (stp high for lxt901a transceiver only) ? link testing enabled (li high) status outputs are grouped at the lower left of the diagram. local status outputs drive led indicators. power and ground pins are shown at the bottom of the diagram. a single power supply is used for both vcc1 and vcc2, with a decoupling capacitor installed between the power and ground busses. an additional power and ground pin (vcca and gnda) is supported in designs using the 64-pin lqfp package. a single power supply is used for all three power and ground pins (vcc1, vcc2, vcca) and (gnd1, gnd2, gnda). install a decoupling capacitor between each power and ground buss. the twisted-pair and aui interfaces are shown at the upper and lower right of the diagram, respectively. impedance matching resistors for 100 utp are installed in each i/o pair and no external filters are required.
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 21 document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 9. lan adapter board - auto port select with external lpbk contro l lxt901a/907a 20 mhz 20 pf 20 pf clki txd tpin 50 50 tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 ten d - connector to aui drop cable chassis gnd fuse 78 78 78 12.4 k tclk rclk rxd cd col lbk paui autosel nth md0 md1 dsqe (907a) stp (901a) li jab plr txd txe txc rxc rxd crs col lbk green red red red ns8390 back-end controller interface loopback enable programming options line status 1 % +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 330 330 330 330 test tpona tponb tpopa tpopb 24.9 1% 24.9 1% bias resistor rbias should be located close to the pin and isolated from other signals. optional: centertap capacitor may improve emc depending on board layout and system design. 2 1 2 1 1 : 1 1 : 2 1 : 1 0.1 f
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 22 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 3.4.2 full-duplex support figure 10 shows the lxt907a transceiver with a texas instruments 380c24 commprocessor. the 380c24 is compatible with mode 4 (md0 and md1 both high). when used with the 380c24, or other full-duplex capable controller, the lxt907a transceiver supports full-duplex ethernet, effectively doubling the available bandwidth of the network. in this application, the sqe function is enabled (dsqe tied low), and the aui port is not used. figure 10. full-duplex operation lxt907a clki txd tpin 50 50 tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 rj45 3 6 8 cin cip don dop din dip rbias gnd2 gnd1 ten 3 12.4 k tclk rclk rxd cd col lbk ledc/fde txd txen txc rxc rxd csn coll lpbk 1 % +3.3 v vcc1 vcc2 clko tms380c24 1 : 2 to 10 base-t twisted- pair network 20 mhz 20 pf 20 pf *test0 1n914 10 k 4 bias resistor rbias should be located close to the pin and isolated from other signals. 1 2 3 4 half/full duplex selection controlled by tms380c24 pin s test0 and outsel0. autosel nth md0 md1 li jab plr green red red programming options line status ledr ledt/pdn ledl 330 330 outsel0 paui 330 1 4.7 k test dsqe (907a) *open collector driver tpona tponb tpopa tpopb 24.9 1% 24.9 1% the tms380c26 may be substituted for dual network support of 10base-t and token ring. optional: centertap capacitor may improve emc depending on board layout and system design. 2 0.1 f
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 23 document number: 249098 revision number: 003 revision date: 27-nov-2005 3.4.3 dual network support - 10base-t and token ring figure 11 shows the lxt901a/907a transceiver with a texas instruments 380c26 commprocessor. the 380c26 is compatible with mode 4 (md0 and md1 both high). when used with the 380c26, both the lxt901a/907a transceiver and a tms38054 token ring transceiver can be tied to a single rj-45, allowing dual network support from a single connector. the lxt901a/907a transceiver aui port is not used. the dsqe pin on the lxt907a transceiver is tied low and the stp pin on the lxt901a transceiver is tied high. figure 11. 380c26 interface for dual network support of 10base-t and token ring lxt901a/907a 20 mhz 20 pf 20 pf clki txd tpin 50 50 tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 tpona tponb tpopb tpopa rj45 3 6 8 from ti tms38054 token ring transceiver cin cip don dop din dip rbias gnd2 gnd1 ten 1 12.4 k tclk rclk rxd cd col lbk paui autosel nth md0 md1 li jab plr txd txe txc rxc rxd crs col lbk green red red red programming options line status 1 % +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 330 330 330 330 380c26 2 to ti tms38054 token ring transceiver 1 : 2 to 10 base-t twisted- pair network bias resistor rbias should be located close to the pi n and isolated from other signals. 1 2 3 additional magnetics and switching logic (not shown) are required to implement the dual network solution. 24.9 1% 24.9 1% test optional: centertap capacitor may improve emc depending on board layout and syst em design. 3 dsqe 907a only stp 901a only 0.1 f
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 24 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 3.4.4 manual port select with link test function with md0 tied low and md1 tied high, the lxt901a/907a transceiver logic and framing are set to mode 3 (compatible with fujitsu mb86950 and mb86960, and seeq 8005 controllers). figure 12 shows the setup for fujitsu controllers. figure 13 on page 25 shows the four inverters required to interface with the seeq 8005 controller. as seen in figure 9 on page 21 both these mode 3 applications show the li pin tied high, enabling link testing; and the stp (lxt901a transceiver only) and nth pins are both tied high, selecting the standard receiver threshold and 100 termination for unshielded tp cable. however, in these applications autosel is tied low, allowing external port selection through the paui pin. figure 12. lan adapter board - manual port select with link test function lxt901a/907a 20 mhz 20 pf 20 pf clki txd tpin 50 50 tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 ten d - connector to aui drop cable chassis gnd fuse 78 78 78 12.4 k tclk rclk rxd cd col lbk paui autosel nth md0 md1 dsqe (907a) stp (901a) li jab plr txd ten tckn rckn rxd xcd lbc red red red mb86950 or mb86960 back-end/ controller interface line status 1 % +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clko 330 330 330 1 : 2 green 330 port selection bias resistor rbias should be located close to the pin and isolated from other signals. test 24.9 1% 24.9 1% xcol optional: centertap capacitor may improve emc depending on board layout and system design. 2 1 1 2 1 : 1 1 : 1 0.1 f
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 25 document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 13. manual port select with seeq 8005 controller lxt901a/907a clki lbk tpin 50 50 tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip rbias gnd2 gnd1 cd d - connector to aui drop cable chassis gnd fuse 78 78 78 12.4 k rxd rclk col ten tclk txd paui autosel nth md0 md1 dsqe (907a) stp (901a) li jab plr red red red line status 1 % +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 330 330 330 1 : 2 green 330 port selection clko 8005 clki lpbk csn rxd rxc coll txen txc txd external 20 mhz source left open bias resistor rbias should be located close to the pin and isolated from other signals. test 24.9 1% 24.9 1% optional: centertap capacitor may improve emc depending on board layout and system design. 2 1 2 1 1 : 1 1 : 1 0.1 f
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 26 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 3.4.5 three media application figure 14 shows the lxt907a transceiver in mode 2 (compatible with intel 82596 controllers) with additional media options for the aui port. two transformers are used to couple the aui port to either a d-connector or a bnc connector. a dp8392 coax transceiver with pm6044 power supply are required to drive the thin coax network through the bnc. figure 14. three media application clki txd tpin 50 tpip 1 : 1 116 14 6 5 4 3 2 1 11 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10base-t twisted- pair network 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop dip rbias gnd2 gnd1 ten d - connector to aui drop cable (thick coax) chassis gnd fuse 78 78 tclk rclk rxd cd col lbk paui autosel nth li md1 md0 jab plr txd rts txc rxc rxd crs cdt lbk 82596 back-end/ controller int erface programming options mode select line status 1 % +3.3 v ledc/fde le dr ledt/pdn ledl vcc1 vcc2 clko 1 : 2 20 mhz system clock clk linktest enable power down 1 2 4 5 7 89 10 12 13 15 16 78 1 2 4 5 7 89 10 12 13 15 16 din cd- cd+ tx- vee tx+ rx- rx+ vee cds txd rxi vee rr- rr+ gnd hbe 1n916 0v bnc to thin coax network 1 k 1% -9v v+ n/c v- 5v 5v en gnd gnd 12 13 9 1 +5 v 2 3 23 1 m 1/2 w 24 test 1.5 k 0.01 f75 f / 1 kv 2 1 bias resistor rbias should be located close to the pin and isolated from other signals. pm6044 dp8392 10 k d s q e ( 9 0 7 a ) 1 0 k f 0 . 1 f 0 . 1 5 0 optional: centertap capacitor may improve emc depending on board layout and system design. 2 4 . 9 1 % 2 4 . 9 1 % lxt907a 2 1 1:1 1:1 1 2 . 4 k
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 27 document number: 249098 revision number: 003 revision date: 27-nov-2005 3.4.6 aui encoder/decoder only in this application ( figure 15 ), the dte is connected to a coaxial network through the aui. autosel is tied low and paui is tied high to manually select the aui port. the twisted-pair port is not used. with md1 and md0 both low, the logic and framing are set to mode 1 (compatible with amd am7990 controllers). the li pin is tied low, disabling the link test function. the dsqe pin is also low, enabling the sqe function on the lxt907a transceiver. the lbk input controls loopback. a 20 mhz system clock is supplied at clk1, with clk0 left open. figure 15. aui encoder/decoder only application lxt907a txd rbias gnd2 gnd1 ten tclk rclk rxd cd col lbk autosel nth md0 md1 dsqe (907a) li jab plr tx tena tclk rclk rx rena clsn lbk red red red am7990 back-end/ controller interface loopback control programming options line status 1 % green +3.3 v ledc/fde ledr ledt/pdn ledl vcc1 vcc2 clki 330 330 330 330 1 2 4 5 7 89 10 12 13 15 16 1 2 3 4 5 6 7 8 15 14 13 12 9 10 11 + 12 v cin cip don dop din dip d - connector to aui drop cable chassis gnd fuse 78 78 78 12.4 k clko paui bias resistor rbias should be located close to the pin and isolated from the other signals 20 mhz left open system clock test 1 1
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 28 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 3.4.7 150 shielded twisted-pair only (lxt901a transceiver only) figure 16 shows the lxt901a transceiver in a typical twisted-pair only application. the dte is connected to a 10base-t network through the twisted-pair rj-45 connector. note that the aui port is not used. with md0 tied high and md1 low, the lxt901a transceiver logic and framing are set to mode 2 (compatible with intel 82596 controllers). a 20 mhz system clock input at clk1 is used in place of the crystal oscillator. (clk0 is left open). the l1 pin externally controls the link test function. the stp and nth pins are both tied low, selecting the reduced receiver threshold and 150 termination for shielded twisted-pair cable. the switch at ledt/pdn manually controls the power down mode. figure 16. 150 shielded twisted-pair only application (lxt901a transceiver ) lxt901a tpin 75 75 tpip 1 : 1 116 14 6 5 4 3 2 1 11 0.1 f 9 tpona tponb tpopb tpopa rj45 3 6 8 to 10 base-t twisted- pair network rbias gnd2 gnd1 paui autosel nth md0 md1 li jab plr ledc/fde ledr ledt/pdn ledl vcc1 vcc2 1 : 2 test 75 1% 37.5 1% 12.4 k 1% 2 20 mhz system clock 82596 back-end/ controller interface clk0 rclk 75 1% 37.5 1% +3.3 v bias resistor rbias should be located close to the pin and isolated from other signals. 2 1 10k line status 10k link test enable programming options stp clk txd rts txc rxc rxd crs cdt lbk clk1 txd ten tclk rclk rxd cd col lbk left open 1 optional: centertap capacitor may improve emc depending on board layout and system design.
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 29 document number: 249098 revision number: 003 revision date: 27-nov-2005 4.0 test specifications note: table 4 through table 13 and figure 17 through figure 42 represent the performance specifications of the lxt901a/907a transceiver. these specifications are guaranteed by test except where noted ?by design.? minimum and maximum values listed in table 6 through table 13 apply over the recommended operating conditions specified in table 5 . for all quality and reliability issues (for example, parts packaging and thermal specifications), please send your questions to intel at the following e-mail address: qr.requests@intel.com . table 4. absolute maximum values parameter symbol min max units supply voltage v cc -0.3 6 v storage temperature t stg -65 +150 oc caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 5. recommended operating conditions parameter symbol min typ max units recommended supply voltage 1 v cc 3.13 3.3 3.47 v recommended operating temperature (commercial) t op 0?+70oc 1. voltages with respect to ground unless otherwise specified. power supply should be filtered to suppress high frequency transients, consistent with good pcb design. table 6. i/o electrical characteristics parameter sym min typ 1 max units test conditions input low voltage 2 v il ??0.8v ? input high voltage 2 v ih 2.0 ? ? v ? output low voltage v ol ??0.4vi ol = 1.6 ma v ol ??10%v cc i ol < 10 a output low voltage (open drain led driver) v oll ??0.7%v cc i oll = 10 ma output high voltage v oh 2.4 ? ? v i oh = 40 a v oh 90 ? ? %v cc i oh < 10 a output rise time tclk & rclk cmos ?? 712nsc load = 20 pf ttl ? ? 7 8 ns ? 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. 2. limited functional tests are performed at these input levels. the majority of functional tests are performed at levels of 0v and 3v.
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 30 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 output fall time tclk & rclk cmos ?? 712nsc load = 20 pf ttl ? ? 7 8 ns ? clki rise time (externally driven) ? ? ? 10 ns ? clki duty cycle (externally driven) ?? 40/60% ? supply current normal mode i cc ? 65 85 ma idle mode i cc ? 95 120 ma transmitting on tp i cc ?95120ma transmitting on aui power down mode i cc ?0.03 2 ma ? table 7. aui electrical characteristics parameter symbol min typ 1 max units test conditions input low current i il ??-700 a? input high current i ih ??500 a? differential output voltage v od 550 ? 1200 mv ? differential squelch threshold v ds 150 250 350 mv 5 mhz square wave input 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. table 8. tp electrical characteristics parameter symbol min typ 1 max units test conditions transmit output impedance z out ?5? ? transmit timing jitter addition 2 ??3.310ns 0 line length for internal mau transmit timing jitter added by the mau and pls sections 2, 3 ??3.35.5ns after line model specified by ieee 802.3 for 10base-t internal mau 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee 802.3 specifies maximum jitter additions at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau. table 6. i/o electrical characteristics (continued) parameter sym min typ 1 max units test conditions 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. 2. limited functional tests are performed at these input levels. the majority of functional tests are performed at levels of 0v and 3v.
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 31 document number: 249098 revision number: 003 revision date: 27-nov-2005 receive input impedance z in ?20 ? k between tpip/tpin, cip/cin & dip/din differential squelch threshold normal threshol d; nth = 1 v ds 300 400 585 mv 5 mhz square wave input reduced threshol d; nth = 0 v ds 180 250 345 mv 5 mhz square wave input table 9. switching characteristics parameter symbol minimum typical 1 maximum units jabber timing maximum transmit time ? 20 ? 150 ms unjab time ? 250 ? 750 ms link integrity timing time link loss receive ? 50 ? 150 ms link min receive ? 2 ? 7 ms link max receive ? 50 ? 150 ms link transmit period ? 8 10 24 ms 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. table 10. rclk/start-of-frame timing parameter symbol minimum typical 1 maximum units decoder acquisition time aui t data ? 900 1100 ns tp t data ?12001500ns cd turn-on delay aui t cd ?25200ns tp t cd ? 425 550 ns receive data setup from rclk mode 1 t rds 60 70 ? ns modes 2, 3 and 4 t rds 30 45 ? ns receive data hold from rclk mode 1 t rdh 10 20 ? ns modes 2, 3 and 4 t rdh 30 45 ? ns rclk shut off delay from cd assert (lxt907a transceiver only; mode 3) tsws ? 100 ? ns 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. table 8. tp electrical characteristics (continued) parameter symbol min typ 1 max units test conditions 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee 802.3 specifies maximum jitter additions at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau.
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 32 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 table 11. rclk/end-of-frame timing parameter type sym mode 1 mode 2 mode 3 mode 4 units rclk after cd off min t rc 51275bt rcv data throughput delay max t rd 400 375 375 375 ns cd turn off delay 2 max t cdoff 500 475 475 475 ns receive block out after ten off typ 1 t ifg 550? ?bt rclk switching delay after cd off (lxt907a transceiver only; mode 3) typ 1 t swe ? ? 120(80) ? ns 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. 2. cd turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last bit. table 12. transmit timing parameter symbol minimum typical 1 maximum units ten setup from tclk t ehch 22 ? ? ns txd setup from tclk t dsch 22 ? ? ns ten hold after tclk t chel 5??ns txd hold after tclk t chdu 5??ns transmit start-up delay - aui t stud ?220450ns transmit start-up delay - tp t stud ?430450ns transmit through-put delay - aui t tpd ??300ns transmit through-put delay - tp t tpd ?300350ns 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing. table 13. collision, col/ci output and loopback timing parameter symbol minimum typical 1 maximum units col turn-on delay t cold ?40500ns col turn-off delay t coloff ?420500ns col (sqe) delay after ten off t sqed 0.65 1.2 1.6 s col (sqe) pulse duration t sqep 500 1000 1500 ns lbk setup from ten t kheh 10 25 ? ns lbk hold after ten t khel 10 0 ? ns 1. typical values are at 25c and are for design aid only, are not guaranteed, and are not subject to production testing.
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 33 document number: 249098 revision number: 003 revision date: 27-nov-2005 4.1 timing diagrams for mode 1 (md1 = low, md0 = low) figures 17 - 22 figure 17. mode 1 rclk/start-of-frame timing figure 18. mode 1 rclk/end-of-frame timing 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data tpip/tpin or dip/din cd rclk rxd t rds t rdh 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff tpip/tpin or dip/din cd rclk rxd t rc
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 34 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 19. mode 1 transmit timing figure 20. mode 1 collision detect timing figure 21. mode 1 col/ci output timing figure 22. mode 1 loopback timing t chel t ehch t chdu ten tclk txd tpo t tpd t dsch t stud t coloff t cold ci col t sqep t sqed ten col t khel t kheh lbk ten
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 35 document number: 249098 revision number: 003 revision date: 27-nov-2005 4.2 timing diagrams for mode 2 (md1 = low, md0 = high) figures 23 - 28 figure 23. mode 2 rclk/start-of-frame timing figure 24. mode 2 rclk/end-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t rds t rdh cd rclk rxd t data tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 t rd tpip/tpin or dip/din cd rclk rxd 1 0 1 0 1 0 1 0 0 t cdoff
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 36 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 25. mode 2 transmit timing figure 26. mode 2 collision detect timing figure 27. mode 2 col/ci output timing figure 28. mode 2 loopback timing t chel t ehch t chdu ten tclk txd tpo t dsch t tpd t stud t coloff t cold ci col t sqed ten col t ifg t sqep t khel t kheh lbk ten
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 37 document number: 249098 revision number: 003 revision date: 27-nov-2005 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) figures 29 - 36 figure 29. mode 3 rclk/start-of-frame timing (lxt901a transceiver) figure 30. mode 3 rclk/end-of-frame timing (lxt901a transceiver) 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t data cd rclk rxd tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd t rd t cdoff cd rclk rxd 1 0 1 0 1 0 1 0 0 tpip/tpin or dip/din 1 0 1 0 1 0 1 0 0 27 bits
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 38 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 31. mode 3 rclk/start-of-frame timing (lxt907a transceiver) figure 32. mode 3 rclk/end-of-frame timing (lxt907a transceiver) 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t data cd rclk rxd tpip/tpin or dip/din 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd t sws recovered from input data stream generated from tclk t rd t cdoff cd rclk rxd t swe recovered clock generated from tclk 1 0 1 0 1 0 1 0 0 tpip/tpin or dip/din 1 0 1 0 1 0 1 0 0
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 39 document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 33. mode 3 transmit timing figure 34. mode 3 collision detect timing figure 35. mode 3 col/ci output timing figure 36. mode 3 loopback timing t chel t ehch t chdu ten tclk txd tpo t stud t dsch t tpd t coloff t cold ci col t sqed ten col t sqep t khel t kheh lbk ten
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 40 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) figures 37 - 42 figure 37. mode 4 rclk/start-of-frame timing figure 38. mode 4 rclk/end-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data cd rclk rxd tpip/tpin or dip/din t rds t rdh 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd tpip/tpin or dip/din cd rclk rxd t cdoff
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 41 document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 39. mode 4 transmit timing figure 40. mode 4 collision detect timing figure 41. mode 4 col/ci output timing figure 42. mode 4 loopback timing t chel t ehch t chdu ten tclk txd tpo t dsch t stud t tpd t coloff t cold ci col t sqep t sqed ten col t khel t kheh lbk ten
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 42 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 5.0 mechanical specifications figure 43. 44-pin plcc dim inches millimeters min max min max a 0.165 0.180 4.191 4.572 a 1 0.090 0.120 2.286 3.048 a 2 0.062 0.083 1.575 2.108 b 0.050 ? 1.270 ? c 0.026 0.032 0.660 0.813 d 0.685 0.695 17.399 17.653 d 1 0.650 0.656 16.510 16.662 f 0.013 0.021 0.330 0.533 44-pin plastic leaded chip carrier ? part number lxt901apc and lxt907apc (commercial temperature range) a 2 a d f a 1 c b d 1 d c l
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 43 document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 44. 64-pin lqfp 64-pin low-profile quad flat package ? part number lxt901alc and lxt907alc (commercial temperature range) dim inches millimeters min max min max a ? 0.063 ? 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 .011 0.17 0.27 d 0.472 bsc 12.00 bsc d1 0.394 bsc 10.00 bsc e 0.472 bsc 12.00 bsc e1 0.394 bsc 10.00 bsc e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 l1 0.039 ref 1.00 ref 311 o 13 o 11 o 13 o 0 o 7 o 0 o 7 o d d 1 a 1 a 2 l a b l 1 3 3 e e 1 e / 2 e
5.1 top-label marking figure 45 shows a sample lqfp package for the lxt901a transceiver. note: in contrast to the pb-free (rohs-compliant) lqfp package, the non-rohs-compliant packages do not have the ?e3? symbol in the last line of the package label. figure 46 shows a sample pb-free rohs-compliant lqfp package for the lxt901a transceiver. figure 45. sample lqfp package ? intel ? djlxt901alc transceiver p in 1 lxt901alc a4 xxxxxxxx part number fpo number bsmc bottom side mark cod e b5392-01 figure 46. sample pb-free (rohs-compliant) lqfp package ? intel ? wjlxt901alc transceiver p in 1 wjlxt901c a4 xxxxxxxx part number fpo number e3 bsmc bottom side mark cod e pb-free indication b5374-01
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 45 document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 47 shows a sample tqfp package for the lxt907a transceiver. in contrast to the pb-free (rohs-compliant) tqfp package, the non-rohs-compliant packages do not have the ?e3? symbol in the last line of the package label. figure 50 shows a pb-free (rohs-compliant) tqfp package for the lxt907a transceiver. figure 47. sample tqfp package ? intel ? djlxt907alc transceiver p in 1 lxt907alc a4 xxxxxxxx part number fpo number bsmc bottom side mark cod e b5419-01 figure 48. sample pb-free (rohs-compliant) tqfp package ? intel ? wjlxt907alc transceiver p in 1 wjlxt907c a4 xxxxxxxx part number fpo number e3 bsmc bottom side mark cod e pb-free indication b5394-01
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 46 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 49 shows a sample plcc package for the lxt901a/907a transceiver. note: in contrast to the pb-free (rohs-compliant) plcc package, the non-rohs-compliant packages do not have the ?e3? symbol in the last line of the package label. figure 50 shows a pb-free (rohs-compliant) plcc package for the lxt901a/907a transceiver. figure 49. sample plcc package ? intel ? nlxt90xapc transceiver p in 1 lxt90xapc a4 xxxxxxxx part number fpo number bsmc bottom side mark cod e b5393-01 figure 50. sample pb-free (rohs-compliant) plcc package ? intel ? eelxt90xapc transceiver p in 1 eelxt90xc a4 xxxxxxxx part number fpo number e3 bsmc bottom side mark cod e pb-free indication b5377-01
intel ? lxt901a/907a universal 3.3 v ethernet transceiver datasheet 47 document number: 249098 revision number: 003 revision date: 27-nov-2005 6.0 ordering information table 14 lists the lxt901a/907a transceivers product ordering information. figure 51 provides the ordering information matrix. table 14. product information intel number revision package type pin count rohs compliant djlxt901alc.a4 a4 lqfp 64 no wjlxt901alc.a4 a4 lqfp 64 yes djlxt907alc.a4 a4 tqfp 32 no wjlxt907alc.a4 a4 tqfp 32 yes nlxt901apc.e2 e2 plcc 44 no eelxt901apc.e2 e2 plcc 44 yes nlxt907apc.e2 e2 plcc 44 no eelxt907apc.e2 e2 plcc 44 yes
intel ? lxt901a/907a universal 3.3 v ethernet transceiver 48 datasheet document number: 249098 revision number: 003 revision date: 27-nov-2005 figure 51 shows an order matrix with sample information for the lxt901a/907a transceivers. figure 51. ordering information matrix ? sample dj c 901a l lxt a4 product revision xn = 2 alphanumeric characters temperature range a = ambient (0 ? 55 0 c) c = commercial (0 ? 70 0 c) e = extended (-40 ? 85 0 c) internal package designator l = lqfp p = plcc n = dip q = pqfp h = qfp t = tqfp b = bga c = cbga e = tbga k = hsbga (bga with heat slug product code xxxxx = 3-5 digit alphanumeric ixa product prefix lxt = phy layer device ixe = switching engine ixf = formatting device (mac/framer) ixp = network processor intel package designator b5326-0 2 pb-free wb bj ja wd qu eg wg ub uc ep ee ru pc el pr lu ew wf jp package leaded sc hqfp tqfp tqfp pqfp pqfp pqfp ssop qfn qfn pdip plcc mmap mmap pbga pbga pbga cbga fcbga tbga pbga hb fa fa hd ku s hg lb pd pa n hz rc fl fw gd gw hf hl tl wj lqfp dj

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